A novel compact model of the product marginal yield and its application for performance maximization

In this paper, we present a novel compact model to calculate the product performance accurately. The compact model is constructed by leakage current and active speed calculation of logic circuit. It becomes possible to estimate marginal yield before pilot wafer by the input of a little Si information (Ring Oscillator frequency, leakage of transistor, wiring capacitance, transistor variability) to the compact model. It is effective to change a transistor target in order to improve marginal yield and maximize product performance. In the case of increasing the CPU frequency by 25% using the same process technology, we can improve marginal yield about 15% by using this method before pilot wafer.