A new Membrane PSOI High Voltage Device with a Buried P+ layer

Author

Yang, Xiao-ming ; Zhang, Bo ; Luo, Xiao-Rong

Author_Institution

Sch. of Microelectron. & Solid State Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2010

Firstpage

785

Lastpage

787

Abstract

A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window results in alleviating significantly SHE. The simulation results show that breakdown voltage of MBP+ SOI is 734V and increases by 548V at L_d=37μm, t_s=4μm and t_I=1μm, in comparison with that of SOI LDMOS. In contrast to Camsei SOI, the maximal surface temperature for MBP+ PSOI decreases by 34K and specific on-resistance reduces by about 44.8%.

Keywords

MIS devices; elemental semiconductors; semiconductor device breakdown; silicon; silicon-on-insulator; SOI LDMOS; breakdown voltage; buried P+ Layer; membrane PSOI high voltage device; partial SOI; silicon substrate; Biomembranes; Breakdown voltage; Electric breakdown; Electric fields; Junctions; Silicon; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667421

Filename

5667421