Title :
A brief survey on power gating design
Author :
Huang, Ping ; Xing, Zuocheng ; Wang, Tianran ; Wei, Qiang ; Wang, Hongyan ; Fu, Guitao
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
With the process scaling down to 65nm, leakage power begin to dominate the power consumption. Power gating as one of the most effective techniques to reduce leakage power has become the research hot spot in the past ten years, and will be applicable in all the future low power design. This paper give a brief summary of the concept of power gating design, the problems when implementing it as well as techniques to deal with them.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; power transistors; leakage power; low power design; power consumption; power gating design; process scaling; size 65 nm; sleep transistor; Algorithm design and analysis; Heuristic algorithms; Microprocessors; Power supplies; Prediction algorithms; Threshold voltage; Transistors; low power; power gating; sleep transistor;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667422
