• DocumentCode
    1631372
  • Title

    A gate-level method for transistor-level bridging fault diagnosis

  • Author

    Fan, Xinyue ; Moore, Will ; Hora, Camelia ; Konijnenburg, Mario ; Gronthoud, Guido

  • Author_Institution
    Dept. of Eng. Sci., Oxford Univ.
  • fYear
    2006
  • Lastpage
    271
  • Abstract
    The paper addresses the issue of transistor-level bridging fault diagnosis. While most of the previous bridging fault diagnosis work focuses on the gate-level bridging faults, this method provides a solution to intra-gate bridging faults diagnosis for the first time. Instead of using any transistor level simulation tools, we develop a transformation technique that allows transistor-level bridging faults to be diagnosed by the commonly used gate-level bridging faults diagnosis tools. Real diagnosis results from Philips designs are presented
  • Keywords
    fault diagnosis; logic arrays; logic gates; transistor-transistor logic; Philips designs; fault diagnosis tools; gate-level method; intra-gate bridging faults diagnosis; transformation technique; transistor level simulation; transistor-level fault diagnosis; Bridges; Costs; Failure analysis; Fault diagnosis; Manuals; Manufacturing; Predictive models; Test pattern generators; Testing; Voting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2006. Proceedings. 24th IEEE
  • Conference_Location
    Berkeley, CA
  • Print_ISBN
    0-7695-2514-8
  • Type

    conf

  • DOI
    10.1109/VTS.2006.6
  • Filename
    1617600