Area and MIT optimization of selective Zigzag power gating

Power Gating(PG) is very effective to reduce the leakage power. Recently proposed Zigzag power gating(ZPG) technique has the visible advantage on short wake-up time. However, additional PG transistors consume intolerable area overhead. Basing on the BPTM-65nm model, we propose a new optimization methodology of the selective ZPG technique for the wide-used dual-threshold voltage CMOS circuit design. We optimize the ZPG area overhead in two steps: First, according to the observation that the leakage of dual-threshold voltage CMOS circuit is mainly origin from logic gates of LVT(low threshold voltage) and DLS (determinant leakage state), we only cut off these gates to reduce the number of gates which need to be turn off. Second, we assign the size of footer and header with a new method to optimize the area overhead further. A large number of experimental data show that on average our method reduces ZPG area overhead from 26.8% to 8.3%, the minimum idle time (MIT) from 3795ps to 2594ps.