Analysis of process impact on local variability thanks to addressable transistors arrays

Author

Cros, A. ; Quemerais, Thomas ; Bajolet, A. ; Carminati, Yann ; Normandon, Philippe ; Kergomard, Flore ; Planes, N. ; Petit, D. ; Arnaud, F. ; Rosa, J.

Author_Institution

TR&D/STD/TPS ECR, STMicroelectron., Crolles, France

fYear

2014

fDate

24-27 March 2014

Firstpage

233

Lastpage

237

Abstract

We designed an addressable transistors array to analyse local variability at the wafer scale. On FDSOI substrates, we measure no impact of the silicon thickness variations on short channel transistors, and demonstrate that the impact on large area transistors is no more visible when the Tsi is well controlled.

Keywords

MOSFET; silicon; silicon-on-insulator; substrates; thickness control; FDSOI substrate; Si; addressable transistors array; controlled Tsi; fully depleted silicon on insulator; large area transistor; local variability; process impact analysis; short channel transistor; silicon film thickness; silicon thickness variation; wafer scale; Logic gates; MOS devices; Silicon; Stochastic processes; Substrates; Transistors; Very large scale integration; SOI; Variability; addressable transistors; matching;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2014 International Conference on

Conference_Location

Udine

ISSN

1071-9032

Print_ISBN

978-1-4799-2193-5

Type

conf

DOI

10.1109/ICMTS.2014.6841498

Filename

6841498

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=163153