A novel methodology of layout design by applying euler path

A new methodology of layout design applying Euler path is proposed. By separating the pFET array and nFET array away, and then mapping them to be diffusion graphs, we can reduce the operational complexity when solving Euler path and generating the stacked layout. The means that making use of adjacency matrix of diffusion graph to identify Euler path and adding dummy edge in advance could make Atallah algorithm simplified. In addition, some optimization to the Atallah algorithm is also investigated.