Title :
A novel methodology of layout design by applying euler path
Author :
Yan, Shaoan ; Li, Dongen ; Wang, Liming ; Xiao, Yongguang ; Tang, Minghua
Author_Institution :
Key Lab. of Low Dimensional Mater. & Applic. Technol., Xiangtan Univ., Xiangtan, China
Abstract :
A new methodology of layout design applying Euler path is proposed. By separating the pFET array and nFET array away, and then mapping them to be diffusion graphs, we can reduce the operational complexity when solving Euler path and generating the stacked layout. The means that making use of adjacency matrix of diffusion graph to identify Euler path and adding dummy edge in advance could make Atallah algorithm simplified. In addition, some optimization to the Atallah algorithm is also investigated.
Keywords :
field effect transistors; graph theory; integrated circuit layout; Atallah algorithm; Euler path; adjacency matrix; diffusion graphs; dummy edge; layout design; nFET array; pFET array; Algorithm design and analysis; Arrays; Complexity theory; Graph theory; Layout; Logic circuits; Presses;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667436
