Title :
Mapper design for an SOI-based FPGA
Author :
Qianli Zhang ; Chen, Stanley L. ; Li, Yan ; Li, Ming ; Chen, Liang
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., Beijing, China
Abstract :
This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining FPGA architectural features and thus improve on the cluster occupancy of the logic resources. The result is proven in extensive test circuits used in our FPGA design. MCNC testbench comparison result is presented.
Keywords :
CMOS digital integrated circuits; SRAM chips; field programmable gate arrays; integrated circuit packaging; silicon-on-insulator; SOI-CMOS process; SRAM-based FPGA; clustering; logic resources; mapper design; packing; size 0.5 micron; user logic netlist; Algorithm design and analysis; Clustering algorithms; Design automation; Field programmable gate arrays; Integrated circuit interconnections; Registers; Table lookup;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667437
