DocumentCode :
1631620
Title :
Mapping of pipeline flow chart onto mesh-based multi-core NoC architecture
Author :
Yang, Haofan ; Xiao, Ruijin ; Liu, Liang ; Jing, Ming-e ; Yu, Zhiyi ; Zeng, Xiaoyang ; Zhou, Dian
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear :
2010
Firstpage :
824
Lastpage :
826
Abstract :
Among current outstanding research problems in NoC Design, mapping application onto NoC is one of the core issues to be explored. In this paper, we propose two methods for mapping a pip elined flow chart onto mesh-based NoC system: Communication Length Concerned (CLC) method and Space Restricted (SR) method after a simple pre-process. The former significantly reduces the latency and energy consumption in inter-core communication while latter method provides a trade-off for run-time mapping based on the former one. Results show that, compared with normal mapping, the CLC method reduces about 43.3% and 28.6% in communication latency and energy consumption, respectively; while the SR method reduces about 37.6% communication latency and 24% energy consumption. The two methods discussed in this paper could be used as guidance for mapping pipeline flow charts on homogenous mesh-based NoC architectures.
Keywords :
energy consumption; network-on-chip; communication latency; communication length concerned method; energy consumption; inter-core communication; mesh-based multicore NoC architecture; network-on-chip; pipeline flow chart mapping; run-time mapping; space restricted method; Computer architecture; Design automation; Energy consumption; Hardware; Pipelines; Shape; Strontium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
Type :
conf
DOI :
10.1109/ICSICT.2010.5667439
Filename :
5667439
Link To Document :
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