A new two-dimensional analytical model for the fully-depleted SOI four-gate transistor

Based on the exact solution of the Poisson´s equation, a new two-dimensional (2-D) model for the silicon-on-insulator (SOI) fully-depleted four-gate transistor(G4-FET) is successfully developed. The model is verified by its good agreement with the numerical simulation of the device simulator. For the threshold voltage degradation, it is found that the lateral coupling effects between lateral gate and front gate and negative vertical coupling effects between back gate and front gate will pull up the threshold voltage significantly. On the other hand, for some junction-gate bias, the positive vertical coupling effects between back gate and front gate will reduce the threshold voltage. The model not only offers the physical insight into the device physics but also provides a basic guidance for designing the the silicon-on-insulator (SOI) four-gate transistor (G4-FET).