Architecture, applications, and design of a video FIR filter IC

The architecture, salient applications, and design method of an experimental video finite impulse response (FIR) digital filter integrated circuit (IC) is described. The authors have used an improved multiplier/accumulator architecture to achieve high throughput and have included hardware to enhance testability. This chip covers many of the frequency filtering, decimation/interpolation, and other one- and two-dimensional digital signal processing applications. There are facilities on the device to allow cascading of several ICs for building higher-order filters or for obtaining other configurations. This very high performance programmable digital FIR filter circuit has been fabricated in 0.9-μm CMOS technology using automatic custom CAD tools. Using such tools as automatic netlist optimizer and automatic layout, the authors created the layout mask from the block diagram in approximately 10 weeks. Although the device was targeted for video frequency applications, it functioned well beyond that range