Title :
Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement
Author :
Shen, Y.-N. ; Lombardi, F.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
The authors present the basic structure of a testable and repairable programmable logic array (PLA) and the design modifications which are required for a full diagnosis and yield enhancement. The testing process is fully analyzed, and the conditions for diagnosis are presented. It is proved that identification in the presence of multiple (crosspoint, stuck-at, and bridging) faults is possible with high coverage. The criteria which permit diagnosis are based on a hierarchical organization of the testing process; significant improvements over previous redundant structures can be achieved. This results in a compact structure with a homogeneous layout which has been evaluated with respect to area overhead for VLSI implementation. Simulation results for benchmark devices are presented. These suggest that an efficient repair of VLSI PLAs for yield enhancement can be achieved
Keywords :
VLSI; automatic testing; fault location; integrated circuit testing; logic CAD; logic arrays; logic testing; production testing; redundancy; VLSI implementation; benchmark devices; bridging; crosspoint; hierarchical organization; homogeneous layout; multiple faults; repair; repairable programmable logic array; stuck-at; testable redundant PLAs; yield enhancement; Automatic testing; Built-in self-test; Circuit faults; Fault detection; Fault diagnosis; Logic devices; Manufacturing; Programmable logic arrays; Redundancy; Very large scale integration;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82354
