Output hazard-free transition tests for silicon calibrated scan based delay testing

Architectural restrictions of scan greatly limit the effectiveness of traditional scan based delay tests. It has been recently shown that additional testing for delays on short paths using fast clocks can significantly lower DPM. However, accurately obtaining the needed timing information for such tests from simulation is extremely difficult. The simulations must not only accurately account for the effects of process parameter variations, but also power supply noise and crosstalk from the excessive switching activity of scan tests. We suggest that learning signal timing information on silicon to "calibrate" such tests can be much more accurate and cost effective. However, such an approach requires that the outputs of the applied tests be hazard free to avoid learning incorrect timing due to a glitch at the output. Simulation results presented here indicate that such output hazard free test can be obtained with an average coverage only about 10% below the transition delay fault coverage for both launch-on-shift (LOS) and launch-on-capture (LOG) modes