Testing of glue logic interconnects using boundary scan architecture

The authors propose test schemes for glue logic (non-boundary-scan components) interconnects. Testing these interconnects is difficult owing to reduced accessibility and glue-logic function-dependent outputs. The proposed schemes address these testability issues and provide efficient boundary-scan based techniques. The tests are applied under the B-Scan DFT (design-for-testability) environment as scan tests. Thus, issues such as ease of test vector generation, test vector loading time, and test application time are very important for the proposed schemes. The application of the test schemes is described