Optimized architecture and design of an output-queued CMOS switch chip

Author

Luijten, Ronald P. ; Abel, François ; Gusat, Mitch ; Minkenberg, Cyriel

Author_Institution

IBM Zurich Res. Lab., Ruschlikon, Switzerland

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

448

Lastpage

453

Abstract

Traditional improvements in packet switch architecture are aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving the architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance. Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory speed requirements and the complexity of wiring needed to connect these memories. Using a property of the combined shared memory and virtual output queuing switch architecture and a property of SRAMs, a new architecture is derived that enables construction of a terabit class switch fabric

Keywords

CMOS memory circuits; SRAM chips; circuit optimisation; electronic switching systems; integrated circuit design; network routing; packet switching; quality of service; queueing theory; shared memory systems; 0.11 micron; QoS; SRAM; fairness; memory speed; optimized architecture; optimized design; output-queued CMOS switch chip; packet switch architecture; placement; routing; shared memory switch architecture; shared-memory switch chips; switch performance; switch utilization; terabit aggregate data rates; terabit class switch fabric; virtual output queuing switch architecture; wiring; Bandwidth; CMOS technology; Design optimization; Packet switching; Registers; Routing; Scalability; Switches; Throughput; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Communications and Networks, 2001. Proceedings. Tenth International Conference on

Conference_Location

Scottsdale, AZ

ISSN

1095-2055

Print_ISBN

0-7803-7128-3

Type

conf

DOI

10.1109/ICCCN.2001.956303

Filename

956303