DocumentCode
1632104
Title
The parallel-test-detect fault simulation algorithm
Author
Underwood, Bill ; Ferguson, Jack
Author_Institution
Microelectron. & Comput. Technol. Corp., Austin, TX, USA
fYear
1989
Firstpage
712
Lastpage
717
Abstract
It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation. Several techniques for implementing a parallel-test-detect simulator are presented, with techniques based on nominator analysis providing the fastest fault simulation results. The dominant-test-detect approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might be used in built-in self-test
Keywords
automatic testing; combinatorial circuits; digital simulation; electronic engineering computing; fault location; logic testing; automatic test pattern generation; automatic testing; built-in self-test; combinational fault simulation; dominant-test-detect; nominator analysis; parallel-patterns; parallel-test-detect fault simulation algorithm; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Concurrent computing; Electrical fault detection; Fault detection; Lifting equipment; Logic functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/TEST.1989.82359
Filename
82359
Link To Document