3-D matrix nano-wire transistor fabrication on silicon substrate

Author

Chan, Mansun ; Ng, Ricky M Y ; Wang, Tao ; Zuo, Xuan ; He, Jin

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2010

Firstpage

883

Lastpage

886

Abstract

A simple top down method to fabricate an array of vertically stacked nanowires is presented. By taking advantage of the non-uniformity of the Inductive Coupled Plasma (ICP) etching process to form a scalloped sidewall followed by a subsequent stress limited oxidation step, a narrow silicon fin can be vertically patterned to form stacked nanowires with different cross-sectional shapes. The stacked nanowires have been used to fabricated Gate-All-Around (GAA) MOSFETs that show excellent characteristics.

Keywords

MOSFET; elemental semiconductors; nanofabrication; nanowires; oxidation; semiconductor quantum wires; silicon; sputter etching; 3D matrix nanowire transistor fabrication; ICP etching; Si; gate-all-around MOSFET; inductive coupled plasma etching; scalloped sidewall structure; silicon fin pattern; silicon substrate; stress limited oxidation; top down method; vertically stacked nanowires; Etching; Logic gates; Nanowires; Oxidation; Shape; Silicon; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667461

Filename

5667461