Title :
Nibble-serial arithmetic processor designs via unfolding
Author :
Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two´s-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W=W1 W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length
Keywords :
computer architecture; digital arithmetic; logic design; microprocessor chips; addition; arithmetic operations; arithmetic processor designs; bit-serial circuits; dedicated high-speed architectures; division; multiplication; nibble-serial implementation; square root; two´s-complement fixed-point number system; unfolding transformation; Adders; Delay lines; Fixed-point arithmetic; Hardware; Process design; Repeaters; Switched circuits; Switches; Switching circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100432
