A novel 10T SRAM cell with low power dissipation in active and sleep mode for write operation

This paper focuses on the analysis of static and dynamic power dissipations and stability analysis of a proposed 10T SRAM cell. In the proposed structure there are two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors are also connected in the pull-down paths which increase the threshold voltages of the transistors and this cause the reduction in sub-threshold leakage current and static power dissipation. Simulation has been done in 45nm CMOS technology with 0.7 volt power supply in Microwind 3.1 software. Simulation results have been compared to those of other existing 10T SRAM cells.