Performance improvement of nc-Si nonvolatile memory by novel design of tunnel and control layer

Author

Qian, Xin-Ye ; Chen, Kun-Ji ; Ma, Zhong-Yuan ; Zhang, Xian-Gao ; Fang, Zhong-Hui ; Liu, Guang-Yuan ; Jiang, Xiao-Fan ; Huang, Xin-Fan

Author_Institution

State Key Lab. of Solid State Microstructures, Nanjing Univ., Nanjing, China

fYear

2010

Firstpage

944

Lastpage

946

Abstract

The nc-Si nonvolatile memory devices with high performance have been fabricated by using general CMOS techniques. High resolution transmission electronic microscope (HRTEM) shows that the average size of nc-Si is 8 nm and its density is 3×10¹¹/cm². The performance of programming/ erasing and retention time is mainly depending on the quality and thickness of tunnel layer and control layer. The results show the relation between the performance and novel design of tunnel and control layers.

Keywords

CMOS integrated circuits; elemental semiconductors; random-access storage; transmission electron microscopy; CMOS technique; HRTEM; high resolution transmission electronic microscope; nc-Si nonvolatile memory device; tunnel layer quality; tunnel layer thickness; CMOS integrated circuits; CMOS technology; Logic gates; Nonvolatile memory; Performance evaluation; Programming; Temperature control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667491

Filename

5667491