Title :
Built in self test of the Macrolan chip
Author :
Illman, Richard ; Clarke, Steve
Author_Institution :
ICL Mainframe Syst. Div., Manchester, UK
Abstract :
The authors describe the experience of implementing self-test in the medium access controller (MAC) chip for the Macrolan advanced fiber-optic local area network system. The CMOS chip contains approximately 35K gates and 200 logic pins, and has been designed using a semi-custom-design approach based on a parameterized cell library. The implementation of BIST (built-in self-test) for this chip has highlighted problems with some conventional BIST techniques and led to the adoption of new test styles. In particular, quasi-exhaustive test has been widely used for testing combinatorial logic within the chip. Also the tradeoffs involved in testing embedded memories and the assumptions on modeling random pattern testing of such memories have been closely investigated. It is concluded that the methodology described allows ASICs (application-specific integrated circuits) to be designed with full BIST
Keywords :
CMOS integrated circuits; application specific integrated circuits; automatic testing; combinatorial circuits; integrated circuit testing; integrated logic circuits; integrated memory circuits; local area networks; logic testing; microprocessor chips; ASICs; BIST; CMOS chip; Macrolan advanced fiber-optic local area network; Macrolan chip; application-specific integrated circuits; built-in self-test; combinatorial logic; embedded memories; logic testing; medium access controller; microprocessor chips; parameterized cell library; quasi-exhaustive test; random pattern testing; semi-custom-design; Automatic testing; Built-in self-test; CMOS logic circuits; Circuit testing; Control systems; Local area networks; Logic gates; Logic testing; Optical fiber LAN; Optical fiber testing;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82362
