DocumentCode
1633071
Title
High voltage JFET with adjustable pinch-off voltage
Author
Hung, C.Y. ; Hu, C.M. ; Gong, J. ; Chan, W.C.
Author_Institution
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2010
Firstpage
963
Lastpage
965
Abstract
A new structure of high-voltage junction FET was designed by using a 40 V LDMOS technology without additional mask in this process. This JFET also has the same breakdown capability as the LDMOSFET. The pinch-off voltage of the JFET was determined by layout, the n-well opening. The pinch-off voltage was almost unchanged with temperature variation. This JFET can be used in circuit applications with varying JFET pinch-off voltages.
Keywords
junction gate field effect transistors; power integrated circuits; adjustable pinch-off voltage; breakdown capability; high voltage JFET; voltage 40 V; Current measurement; JFETs; Junctions; Logic gates; MOSFETs; Temperature measurement; Voltage measurement; JFETs; LDMOS; Pinch-off;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667500
Filename
5667500
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