A pragmatic approach to the design of self-testing circuits

Author

Savaria, Yvon ; Lague, Bruno ; Kaminska, Bozena

Author_Institution

Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada

fYear

1989

Firstpage

745

Lastpage

754

Abstract

A tool for interactively finding hard-to-test nodes and assessing the impact of test points on random pattern testability is described. With this tool, a set of test points which bring the fault coverage to almost 100% was found for the hardest ISCAS benchmark. It is shown that observation test points only are not sufficient, and thus controllable test points are required. The added test points yield test sets shorter than those necessary with weighted random test sets. On the basis of these findings, a pragmatic approach to built-in self-test (BIST) is proposed. New CMOS BILBO-like test latches that are self-tested are also proposed. A modified implementation for the force-observe (F-O) test points is proposed, and an evaluation of the relative overhead associated with both the circular scan path and the added test points is presented

Keywords

CMOS integrated circuits; VLSI; integrated circuit testing; logic design; logic testing; BIST; CMOS BILBO-like test latches; ISCAS benchmark; VLSI force observe test points; circular scan path; controllable test points; hard-to-test nodes; logic testing; observation test points; random pattern testability; relative overhead; self-testing; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Latches; Logic testing; Programmable logic arrays; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82363

Filename

82363