Title :
A BIST design methodology experiment
Author :
Duncan, Samuel H.
Author_Institution :
Digital Equipment Corp., Littleton, MA, USA
Abstract :
The author describes an experiment in which built-in self-test (BIST) was added to existing gate-array probe designs and simulation was used to easily identify controllability and visibility problems. He documents investigations of ECL (emitter coupled logic) gate arrays to study the advantages and costs of using BIST. The first goal of this experiment was to develop a set of rules or a design methodology that would make it possible to implement these BIST test cases without undue effort. The second was to measure the effectiveness of BIST by fault simulation. The third was to document the cost in power, pins, gates, and computer resources in the design environment. Three test case designs were chosen for this experiment such that the results would be as representative as possible
Keywords :
economics; emitter-coupled logic; fault location; logic CAD; logic arrays; logic testing; BIST design; ECL; built-in self-test; controllability; costs; effectiveness; emitter coupled logic; fault simulation; gate arrays; logic CAD; visibility; Built-in self-test; Computational modeling; Controllability; Costs; Design methodology; Logic arrays; Logic gates; Pins; Probes; Testing;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82364
