On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs

Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems.