Title :
A high performance junctionless PTGVMOS with native tie for deca- nanometer regime
Author :
Chang, Yu-Che ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Lin, Po-Hsieh
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, Ion/Ioff ~ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for JPTGV fabrication and it can be employed for use in deca-nanometer regime.
Keywords :
MOSFET; interface states; p-n junctions; JPTGV fabrication; PTGV MOSFET; deca-nanometer regime; electrical characteristics; high performance junctionless PTGVMOS; low interface trap density; native tie; numerical analysis; p-n junctions; pseudo tri-gate vertical MOSFET; subthreshold swing; Delay; Fabrication; Logic gates; P-n junctions; Performance evaluation; Thermal degradation; Thermal stability;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667520
