Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough?

Interest in asynchronous circuits has increased in the VLSI research community due to the growing limitations faced during the design of synchronous circuits, which often result in over constrained design and operation. Albeit a wide variety of techniques for designing asynchronous circuits are available, quasi-delay-insensitive approaches are often preferable due to their simple timing analysis and closure. Null Convention Logic is a style that supports quasi-delay-insensitive design and enables power-, area- and speed-efficient circuits using a standard-cell methodology. However, the correct functionality of such circuits can be jeopardized by transients caused by single event effects, which can generate single event upsets. This work evaluates how Schmitt triggers on output inverters can help mitigating such problems in Null Convention Logic gates and if this approach is sufficient.