A 5.7-GHz low-power and high-gain 0.18-/spl mu/m CMOS double-balanced mixer for WLAN

Author

Liao, C.-H. ; Chu, Y.-K. ; Huang, D.-R. ; Chuang, H.-R.

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan

fYear

2005

Firstpage

265

Lastpage

267

Abstract

This paper presents a low-power and high-gain 5.7 GHz CMOS double-balanced mixer for an IEEE 802.11a WLAN application. The RF input frequency of the mixer is 5.725 ~ 25 GHz, LO is 5.265 ~ 5.325 GHz, IF is at 480 MHz. The mixer is fabricated with the 0.18 mum 1P6M standard CMOS process. The die size is 0.627 times 0.649 mm². The measurements are performed using an FR-4 PCB test fixture. The fabricated mixer exhibits a conversion gain of 11 dB, noise figure of 12.8 dB, and input P_1dB -16.4 dBm. The DC consumption current is 2.0 mA /1.0 mA for the core/buffer amplifier at V_DD = 1.8 V

Keywords

CMOS integrated circuits; DC amplifiers; MMIC mixers; low-power electronics; wireless LAN; 0.18 mum; 1 mA; 1.8 V; 12.8 dB; 1P6M standard CMOS process; 2 mA; 480 MHz; 5.7 GHz; DC consumption current; FR-4 PCB test fixture; IEEE 802.11a WLAN application; RF input frequency; core-buffer amplifier; low-power high-gain CMOS double-balanced mixer; Baseband; CMOS process; Circuits; Costs; Linearity; Mixers; Noise figure; Radio frequency; Switches; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Technology, 2005. The European Conference on

Conference_Location

Paris

Print_ISBN

2-9600551-1-X

Type

conf

DOI

10.1109/ECWT.2005.1617708

Filename

1617708