Flexible hardware architecture for multi-media communications processing

A microprocessor with features designed specifically for digital signal processing and communications protocol processing, for applications in data transmission relative to multiple media access, is described. In comparison with current microprocessors, this processor has efficient and cost-effective computation power to meet the needs of future devices for integration of high-throughput multimedia networks. Current state of the art in media integration technology is discussed and objectives for a new processor architecture are described. Specific parameters that contribute to the performance of multimedia adapters are identified. A set of instructions has been developed to meet the objectives, and each component of the new architecture is explained with respect to the mechanism for implementation. A single-cycle parallel multiplier provides the digital signal processing ability for voice and video processing. A frame and header processing unit provides a structure to enhance layered protocol processing and elements to facilitate encryption and data compression. Justifications for the techniques are provided and the advantages over existing technology are discussed. A brief discussion indicates how such a processor would apply to future network interfaces along with possible future trends