Intelligent system for detecting cardiac arrhythmia on FPGA

This paper presents a hardware implementation of the detection system of cardiac arrhythmias on FPGA. Thus we are interested in the software and hardware detection of the QRS complex. Our algorithm is based around a recursive digital filters (FIR) and non-recursive (IIR). The hardware implementation of our algorithm was done in HDL (hardware description language). For this our generated source has been simulated, synthesized and tested on Xilinx FPGA (Field Programmable Gate Array) card using the MIT BIH data base. The results shows the contribution of this implementation for embedded systems to better track patients by minimizing the size of the screen and increasing the computational efficiency while reducing the execution time.