Power dissipation analysis for island-style FPGA architecture

In this paper, we consider FPGA architecture optimization to reduce power consumption. We study two FPGA routing architectures. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexors. Experimentation shows that when we use bidirectional SB based on tri-states and multiplexers, power is reduced by 47% compared to SB implemented using back-to-back tri-state drivers. Furthermore, we show that larger circuits tend to realize larger power savings.