A memory-saved and polynomial-based timing simulator for all-digital receivers

Generally, the VCXO used in timing recovery is an analog device, so it is difficult to simulate the sampling error and to integrate the timing blocks with the system simulation. This paper presents a memory-saved and polynomial-based timing simulator for all-digital receivers. The Farrow structure is adopted in the simulator. The structure of the simulator is easy to carry out in time sequence simulation; furthermore, the simulator can be implemented in hardware. And it can be applied to all kinds of all-digital receivers. It is very convenient to test the interaction between timing algorithm and the other blocks, such as carrier recovery, equalizer and channel decoder etc.