Title :
Dynamic partial reconfiguration of the Ubichip for implementing adaptive size incremental topologies
Author :
Satizábal, Héctor F. ; Upegui, Andres
Author_Institution :
Univ. de Lausanne, Lausanne
Abstract :
The Ubichip is a reconfigurable digital circuit with special bio-inspired mechanisms that supports dynamic partial reconfigurability in a flexible and efficient way. This paper presents an adaptive size neural network model with incremental learning that exploits these capabilities by creating new neurons and connections whenever it is needed and by destroying them when they are not used during some time. This neural network, composed of a perception layer and an action layer, is validated on a robot simulator, where neurons are created under the presence of new perceptions. Furthermore, links between perceptions and actions are created, reinforced, and destroyed following a Hebbian approach. In this way, the neural controller creates a model of its specific environment, and learns how to behave in it. The neural controller is also able to adapt to a new environment by forgetting previously unused knowledge, freeing thus hardware resources.We present some results about the neural controller and how it manages to characterize some specific environments by exploiting the dynamic hardware topology support offered by the ubichip.
Keywords :
digital circuits; network topology; neural nets; Hebbian approach; Ubichip; adaptive size incremental topology; adaptive size neural network; dynamic partial reconfiguration; incremental learning; neural controller; reconfigurable digital circuit; Adaptive systems; Circuit topology; Digital circuits; Environmental management; Hardware; Knowledge management; Network topology; Neural networks; Neurons; Robots;
Conference_Titel :
Evolutionary Computation, 2009. CEC '09. IEEE Congress on
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-2958-5
Electronic_ISBN :
978-1-4244-2959-2
DOI :
10.1109/CEC.2009.4982940