SIMPAC: a simulator for parallel architectures and computing

Author

Arunkumar, S. ; Lal, R. ; Venkatagopal, R. ; Parekh, R.G. ; Daruwala, R.D.

Author_Institution

Indian Inst. of Technol., Bombay, India

fYear

1992

Firstpage

196

Abstract

An event-driven simulator for performance evaluation and modeling of parallel processing systems and parallel algorithms is presented. The system topology and architectural details are input to the simulator by means of a menu-driven graphics interface. The application program to be simulated is written in the metalanguage provided and mapped onto the system. The simulator produces performance metrics of resource utilization and process sojourns in various states. A trace file containing the log of the system, execution snapshots, and a module for graphical execution animation is provided for further analyses

Keywords

digital simulation; parallel algorithms; parallel architectures; application program; event-driven simulator; execution snapshots; graphical execution animation; menu-driven graphics interface; metalanguage; parallel algorithms; parallel architectures; parallel computing; parallel processing systems; performance evaluation; performance metrics; resource utilization; system topology; trace file; Computational modeling; Concurrent computing; Discrete event simulation; Graphics; Measurement; Parallel algorithms; Parallel architectures; Parallel processing; Resource management; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.

Conference_Location

Melbourne, Vic.

Print_ISBN

0-7803-0849-2

Type

conf

DOI

10.1109/TENCON.1992.271956

Filename

271956