Title :
Parallel solution of piecewise-linear transistor circuits
Author :
Haji, I.N. ; Tejayadi, O.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
The implementation of a dynamic partitioning and solution method for the simulation of transistor circuits on a shared memory parallel computer is presented. Transistor characteristics are represented by piecewise-linear curves. Partitioning and partition updating are done by region number comparisons coupled to a parallel clustering algorithm. Partitioning results in completely DC decoupled subcircuits, which are then solved in parallel. When small floating capacitances (Miller capacitance) are included and not considered during partitioning, a Gauss-Jacobi method is applied for efficient use of processors. Simulation on an Alliant FX/8 computer with eight processors has shown speed improvements of six times compared to one processor
Keywords :
circuit analysis computing; nonlinear network analysis; parallel algorithms; piecewise-linear techniques; transistor circuits; Alliant FX/8 computer; DC decoupled subcircuits; Gauss-Jacobi method; Miller capacitance; computer aided analysis; dynamic partitioning; floating capacitances; parallel clustering algorithm; partition updating; piecewise-linear transistor circuits; region number comparisons; shared memory parallel computer; simulation; Capacitance; Circuit simulation; Clustering algorithms; Computational modeling; Computer simulation; Concurrent computing; Coupling circuits; Gaussian processes; Partitioning algorithms; Piecewise linear techniques;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100442
