Parallel solution of piecewise-linear transistor circuits

The implementation of a dynamic partitioning and solution method for the simulation of transistor circuits on a shared memory parallel computer is presented. Transistor characteristics are represented by piecewise-linear curves. Partitioning and partition updating are done by region number comparisons coupled to a parallel clustering algorithm. Partitioning results in completely DC decoupled subcircuits, which are then solved in parallel. When small floating capacitances (Miller capacitance) are included and not considered during partitioning, a Gauss-Jacobi method is applied for efficient use of processors. Simulation on an Alliant FX/8 computer with eight processors has shown speed improvements of six times compared to one processor