DocumentCode
1634681
Title
FAST-CBL: a fast floorplanning algorithm based on corner block list representation
Author
Yijie Seng ; Dong, Sheqin ; Hong, Xianlong ; Zeng, Yijie
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Volume
2
fYear
2004
Firstpage
1213
Abstract
We present FAST-CBL, a fast floorplanning algorithm based on corner block list representation. By reusing the common largest sub-floorplan of the floorplans of two neighboring solutions in the annealing process, FAST-CBL reduces the overall computations, and thus achieves a significant improvement over the original algorithm. Both theoretical analysis and experimental results demonstrate that our floorplanning algorithm is quite efficient.
Keywords
VLSI; circuit layout CAD; integrated circuit layout; simulated annealing; VLSI physical design; annealing process; corner block list representation; fast floorplanning algorithm; simulated annealing; Algorithm design and analysis; Circuit simulation; Computational modeling; Computer science; Integrated circuit technology; Simulated annealing; Space exploration; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on
Print_ISBN
0-7803-8647-7
Type
conf
DOI
10.1109/ICCCAS.2004.1346393
Filename
1346393
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