Title :
A normalized configuration of floorplans and ABLR-relations
Author :
Zhang, Xuliang ; Kajitani, Yoji
Author_Institution :
Jedat Innovation Inc., Kitakyushu, Japan
Abstract :
The single-sequence (SS) debuted very recently as the literally simplest code to represent the consistent ABLR-relations (above, below, left-of, right-of) between every pair of objects. It is evolutional in several senses in that it does not convey the labels of objects and that objects could be either physical modules or topological rooms of a T-junction floorplan. Rather it is considered an extremal abstraction of those BSG, SP, O-Tree, etc. algorithms (for packing) and Q-seq, CBL, HPG, etc. (for floorplanning). The paper reports a discovery of a particular relation between SS and the normalized configuration of the floorplan called the unit-diagonal diagram.
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network topology; system-on-chip; T-junction floorplan; VLSI layout; floorplanning algorithms; packing algorithms; physical modules; single-sequence; system-on-chip; topological rooms; unit-diagonal diagram; Compaction; Data structures; Helium; Productivity; Technological innovation; Time factors; Timing; Tin; Very large scale integration;
Conference_Titel :
Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on
Print_ISBN :
0-7803-8647-7
DOI :
10.1109/ICCCAS.2004.1346394
