DocumentCode :
1634733
Title :
An algorithm for checking slicing floorplan based on HPG and its application
Author :
Zhuang, Changwen ; Zhu, Xiaoke ; Takashima, Yasuhiro ; Nakatake, Shigetoshi ; Kajitani, Yoji
Author_Institution :
Res. & Dev. Div., JEDAT Innovation Inc., Kitakyushu, Japan
Volume :
2
fYear :
2004
Firstpage :
1223
Abstract :
The slicing floorplan has been intensively researched for its naive property to cut-based placement, soft-module packing, designers´ intention even after packing and general floorplan representations were proposed. HPG, one easy-to-understand general floorplan representation, was proved to get the optimal solution in a shorter time than other representations. In this paper, we present an algorithm to show another outstanding feature of HPG. By using this algorithm, we can search and find the optimal slicing floorplan easily, which can provide more flexibility for placement and routing tools. Experiments show the effectiveness and promising perspective of our algorithm.
Keywords :
circuit layout CAD; circuit optimisation; network routing; HPG; cut-based placement; general floorplan representation; optimal solution; placement tools; routing tools; search; slicing floorplan; soft-module packing; Algorithm design and analysis; Circuits; Crosstalk; Routing; Runtime; Simulated annealing; Technological innovation; Temperature; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on
Print_ISBN :
0-7803-8647-7
Type :
conf
DOI :
10.1109/ICCCAS.2004.1346395
Filename :
1346395
Link To Document :
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