An incremental placement algorithm for building block layout design based on the O_tree non-slicing representation

Author

Li, Jing ; Yu, Juebang ; Miyashita, Hiroshi

Author_Institution

Coll. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

Volume

2

fYear

2004

Firstpage

1248

Abstract

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O_tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, we present an incremental placement algorithm for BBL (building block layout) design in VLSI physical design. The good performance of experimental results in dealing with instances taken from industry proves the effectiveness of our algorithm.

Keywords

VLSI; circuit layout CAD; integrated circuit layout; network topology; optimisation; trees (mathematics); VLSI physical design; building block layout design; incremental placement algorithm; nonslicing floorplans; ordered tree nonslicing representation; topological representations; Algorithm design and analysis; Circuits; Design methodology; Design optimization; Educational institutions; Electronics industry; Iterative algorithms; Iterative methods; Partitioning algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on

Print_ISBN

0-7803-8647-7

Type

conf

DOI

10.1109/ICCCAS.2004.1346400

Filename

1346400