AL/RTL co-modeling and general test generation

Current hardware/software co-design and SOC design often need to handle system descriptions at different abstraction levels. This requires a unified modeling method across the levels to facilitate design validation. This paper addresses the problem of co-modeling across algorithmic level (AL) and register transfer level (RTL). A constraint satisfaction problem (CSP) is utilized to do the modeling. We give a framework on how to do general test generation based on this co-modeling technique with a constraint logic programming (CLP) tool as the problem-solving engine. By experimenting on an example we built, we demonstrate the application of co-modeling method.