A practical high-speed image processor for automated visual inspection system

A practical architecture of a image processor for high-speed automated visual inspection (AVIS) is proposed. Some of the fundamental functions are enhanced to make the most of the architecture, which aims at the solution of the tradeoff problem between high-speed processing capability and flexibility to cope with various requirement specifications of AVIS. The architecture is based on a raster-scanning pipeline processing hardware module which utilizes look-up tables (LUTs) for the image processing and the control of feature extraction. It is composed of two loops of data processing flow: one is for usual image processing, while the other is for transmission of the LUT data and extracted features data. Since the architecture makes the data go through each other´s bus, it can process the extracted feature data as equivalently as image data and can also use the processed image and feature data as LUT data