DocumentCode
1635357
Title
An Efficient Heuristic for Minimizing Maximum Lateness on Parallel Batch Machines
Author
Chiang, Tsung-Che ; Cheng, Hsueh-Chien ; Fu, Li-Chen
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei
Volume
2
fYear
2008
Firstpage
621
Lastpage
627
Abstract
Batch machines are common in many complex manufacturing systems like wafer fabrication facilities. They are characterized by multiple capacity and long processing times, and thus scheduling of them is important for raising the performance of the entire system. In this paper, we address the identical parallel batch machine scheduling problem considering incompatible job families and dynamic job arrivals. A local search-based heuristic is proposed to minimize maximum lateness. Performance of the proposed heuristic is compared with a state-of-the-art genetic algorithm-based approach, and the experimental results show that our approach is better than the benchmark approach in terms of both solution quality and computational efficiency.
Keywords
batch processing (industrial); genetic algorithms; manufacturing systems; computational efficiency; dynamic job arrivals; genetic algorithm; local search-based heuristic; manufacturing systems; parallel batch machine scheduling; wafer fabrication facilities; Application software; Computer science; Design engineering; Dynamic scheduling; Fabrication; Intelligent manufacturing systems; Job shop scheduling; Machine intelligence; Manufacturing systems; Processor scheduling; batch machines; dynamic job arrival; incompatible families; local search; maximum lateness;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Systems Design and Applications, 2008. ISDA '08. Eighth International Conference on
Conference_Location
Kaohsiung
Print_ISBN
978-0-7695-3382-7
Type
conf
DOI
10.1109/ISDA.2008.73
Filename
4696403
Link To Document