A 33 Mflops Floating Point Processor Using Redundant Binary Representation

Author

Edamatsu, H. ; Taniguchi, T. ; Nishiyama, T. ; Kuninobu, S.

Author_Institution

Matsushita Semiconductor Research Center, Osaka, Japan

fYear

1988

Firstpage

152

Keywords

Adders; Arithmetic; Circuits; Clocks; Delay; Ducts; Pipeline processing; Process design; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International

Conference_Location

San Francisco, CA, USA

Type

DOI

10.1109/ISSCC.1988.663676

Filename

663676

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