On the design and test of asynchronous macros embedded in synchronous systems

The design of synchronously testable asynchronous macros is investigated. A novel implementation model which uses an explicit state register is presented. This approach makes it possible to apply scan and boundary tests to nonsynchronous VLSI systems. The state register is composed of SR (set-reset) flip-flops, which can operate in asynchronous, synchronous, and (token) scan mode. It is shown that these controllers are synchronously testable and can be derived directly from a control graph description. The approach is exemplified by the design and test of a self-timed ALU (arithmetic and logic unit)