Title :
Modeling and simulation for NBTI-considered path delay prediction in logical circuit
Author :
Yao Lin ; Xiaojin Li ; Yanling Shi
Author_Institution :
Dept. of Electron. Eng., East China Normal Univ., Shanghai, China
Abstract :
NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on the conventional reaction-diffusion (R-D) model which is used to predict the threshold voltage shift (ΔVTH) of p-type MOSFET. Besides load capacitance (CL), input slew rate (ti) and supply voltage (VDD), ΔVTH versus gate delay degradation of NAND, INV, and NOR have been evaluated and approximated by second-order polynomials. Furthermore, a method to calculate the degradation of circuit speed over a long period of time given input switching rate, duty factor and power supply, is built up. Finally, the effectiveness of the proposed has been demonstrated with the ISCAS´85 benchmark circuit.
Keywords :
MOSFET; logic circuits; logic gates; negative bias temperature instability; polynomials; reaction-diffusion systems; INV gate; ISCAS´85 benchmark circuit; NAND gate; NBTI degradation; NBTI-considered path delay prediction; NOR gate; R-D model; gate delay degradation; input slew rate; load capacitance; logic gates; logical circuit; long-time circuit performance; negative bias temperature instability; p-type MOSFET; reaction-diffusion model; second-order polynomials; supply voltage; threshold voltage shift; Degradation; Delays; Equations; Integrated circuit modeling; Logic gates; Mathematical model; Predictive models;
Conference_Titel :
Junction Technology (IWJT), 2014 International Workshop on
Conference_Location :
Shanghai
DOI :
10.1109/IWJT.2014.6842033
