A novel VLSI architecture for ACS operation in adaptive Viterbi decoding

The trend in wireless communication systems has indicated the need to dynamically adapt communication hardware architectures according to the runtime physical environment. The adaptive Viterbi algorithm, which adaptively computes the survivor path according to the channel environment, reduces the computation of complexity and correspondingly power consumption greatly. In this paper, the authors present a novel VLSI architecture for the add-compare-select (ACS) unit, which is the key component of the adaptive Viterbi decoder. In the proposed scheme, the compare unit is simplified from the variable based to constant based by employing a simple transform to the adaptive Viterbi algorithm. Based on the simplicity of the constant comparison circuit, we develop a parallel approach to select N_max paths out of 2N_max possible paths. The proposed transformed architecture eliminates the need for path metric storage unit and reduces the complexity of the comparison operation. The proposed ACS architecture achieves 57 %, 47 % and 7 % improvement in power, area and speed respectively compared to the conventional approach. Moreover, there is a 25 % to 47 % storage reduction in the path metric unit (PMU).