A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet

A high-throughput and high-reliable physical-layer architecture for very-short-reach (VSR) and backplane Ethernet applications was developed. VSR and backplane networks provide 100-Gb/s data transmission between blade servers and LAN switches. This architecture supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, making it well suited to VSR and backplane applications for inter-LAN-switch and intra-cabinet networks. Its links comprise ten 10-Gb/s highspeed serial lanes. Payload data are transmitted by a ribbon fiber and a copper cable for VSR applications and by copper channels for the backplane board. Ten lanes convey Ethernet data frames and parity data of forward-error correction code (newly developed (544, 512) code FEQ, providing highly reliable (BER<lE-22) data transmission with a burst-error correction with low latency (i.e., 29.0 ns on the transmitter (Tx) side and 104.4 ns on the receiver (Rx) side). A 64B/66B code-sequence-based skew compensation mechanism, which provides low-latency compensation for the lane-to-lane skew, is used for multi-lane serial transmission. Testing an ASIC with this physical-layer architecture showed that it can provide 100-Gb/s data transmission with a 747-kgate circuit, which is small enough to be implemented in a single LSI. Furthermore in this paper, insufficient FEC rate in past report was solved, and a technique for improving reliability of the above compensation mechanism was proposed.