Synthesis of self-clocked asynchronous state machines

A systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding is described. Multiple input changes are allowed. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in small scale integration (SSI) or VLSI. It avoids extra delay elements often necessary in self-clocked circuits. The method is illustrated by its application to the design of a VMEbus requester