In-situ measurements of polycrystalline silicon feature voltages for investigation of the notching effect during plasma etching

Summary form only given. A significant problem in poly-silicon etching of submicron features is "notching" of polycrystalline silicon lines. Poly-silicon is used to make the gate connection of CMOS transistors. Its configuration is in lines, similar to the metal lines on a device. "Notching" is the detrimental erosion of this line at its base. It occurs during the "overetch" period at the end of the etching step. Severe notching of poly lines can lead to problems such as increased line resistance and delamination of poly lines. Line-and-space test structures are used to measure the potentials of individual poly lines. Test structures are 0.5 um and 0.75 um line-and-space structures of silicon dioxide on poly-silicon on a silicon dioxide base, with aspect ratios ranging from 1.6 to 3. Measurement of the lines\´ potentials are made in-situ, in an Argon inductively coupled plasma at 13.56 MHz.