III–V MOSFETs: Surface passivation for gate stack, source/drain and channel strain engineering, self-aligned contact metallization

In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering. InGaAs FETs with high-stress liner stressor were also realized. A CMOS-compatible salicide-like process was developed for self-aligned contact metallization. We also explore the integration of III-V on Si platform for potential device integration.